// ******************************************************************************
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  jpg_cvdr_reg_nmanager_reg_offset.h
// Project line  :
// Department    :  K3
// Version       :  1.0
// Date          :  2013/5/31
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2
// History       :  2018/03/16 17:38:29 Create file
// ******************************************************************************

#ifndef __JPG_CVDR_REG_NMANAGER_REG_OFFSET_H__
#define __JPG_CVDR_REG_NMANAGER_REG_OFFSET_H__

/* jpg_cvdr_reg_nmanager Base address of Module's Register */
#define SOC_jpg_cvdr_reg_nmanager_BASE                       (0x0)

/******************************************************************************/
/*                      SOC jpg_cvdr_reg_nmanager Registers' Definitions                            */
/******************************************************************************/

#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_CVDR_CFG_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x0)    /* CVDR config register. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_CVDR_DEBUG_EN_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x4)    /* CVDR debug register enable. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_CVDR_DEBUG_REG       (SOC_jpg_cvdr_reg_nmanager_BASE + 0x8)    /* CVDR debug register. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_CVDR_WR_QOS_CFG_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0xC)    /* AXI Write QOS/Pressure configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_CVDR_RD_QOS_CFG_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x10)   /* AXI Read QOS/Pressure configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_FORCE_CLK_REG        (SOC_jpg_cvdr_reg_nmanager_BASE + 0x14)   /* Force clock ON */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_OTHER_RO_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x20)   /* Spare Other RO. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_OTHER_RW_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x24)   /* Spare Other RW. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_VP_WR_CFG_2_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x50)   /* Video port write Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_VP_WR_AXI_FS_2_REG   (SOC_jpg_cvdr_reg_nmanager_BASE + 0x54)   /* AXI address Frame start. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_VP_WR_AXI_LINE_2_REG (SOC_jpg_cvdr_reg_nmanager_BASE + 0x58)   /* AXI line wrap and line stride. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_VP_WR_IF_CFG_2_REG   (SOC_jpg_cvdr_reg_nmanager_BASE + 0x5C)   /* Video port write interface configuration: prefetch or reset or stall capability. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_VP_WR_2_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x838)  /* Video port write Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_CFG_4_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1370) /* Initiator write Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_DEBUG_4_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1374) /* Non-Raster Write DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_WR_4_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1378) /* NR WR Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_CFG_5_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1380) /* Initiator write Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_DEBUG_5_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1384) /* Non-Raster Write DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_WR_5_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1388) /* NR WR Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_CFG_8_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x13B0) /* Initiator write Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_DEBUG_8_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x13B4) /* Non-Raster Write DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_WR_8_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x13B8) /* NR WR Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_CFG_9_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x13C0) /* Initiator write Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_WR_DEBUG_9_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x13C4) /* Non-Raster Write DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_WR_9_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x13C8) /* NR WR Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_CFG_2_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1550) /* Initiator read Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_DEBUG_2_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1554) /* Non-Raster Read DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_RD_2_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1558) /* NR RD Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_CFG_4_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1570) /* Initiator read Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_DEBUG_4_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1574) /* Non-Raster Read DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_RD_4_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1578) /* NR RD Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_CFG_5_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1580) /* Initiator read Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_DEBUG_5_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1584) /* Non-Raster Read DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_RD_5_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1588) /* NR RD Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_CFG_8_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x15B0) /* Initiator read Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_DEBUG_8_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x15B4) /* Non-Raster Read DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_RD_8_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x15B8) /* NR RD Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_CFG_9_REG      (SOC_jpg_cvdr_reg_nmanager_BASE + 0x15C0) /* Initiator read Configuration. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_NR_RD_DEBUG_9_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x15C4) /* Non-Raster Read DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_LIMITER_NR_RD_9_REG  (SOC_jpg_cvdr_reg_nmanager_BASE + 0x15C8) /* NR RD Access limiter. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_SPARE_0_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1D30) /* Spare. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_SPARE_1_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1D34) /* Spare. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_SPARE_2_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1D38) /* Spare. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_SPARE_3_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1D3C) /* Spare. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_VP_WR_DEBUG_2_REG    (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1D48) /* Video Port Write DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_0_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F40) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_1_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F44) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_2_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F48) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_3_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F4C) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_4_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F50) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_5_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F54) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_6_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F58) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_7_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F5C) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_8_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F60) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_9_REG          (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F64) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_10_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F68) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_11_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F6C) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_12_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F70) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_13_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F74) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_14_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F78) /* DEBUG information. */
#define SOC_jpg_cvdr_reg_nmanager_AXI_JPEG_DEBUG_15_REG         (SOC_jpg_cvdr_reg_nmanager_BASE + 0x1F7C) /* DEBUG information. */

#endif // __JPG_CVDR_REG_NMANAGER_REG_OFFSET_H__
